1. Field of the Invention
The present invention relates in general to memory arrays and relates more specifically to sense amplifiers for low voltage memory arrays.
2. Description of the Related Art
Memory devices, such as Dynamic Random Access Memory (DRAM) devices, are commonly used to store information in integrated circuits. A conventional DRAM device includes a plurality of individual memory cells configured in an array. A memory array typically comprises a configuration of intersecting rows and columns, referred to as word lines and bit lines, respectively. The word lines and bit lines are fabricated as metal lines on an integrated circuit and are coupled to the memory cells for accessing the data stored in the memory cells.
Typically, each memory cell in the array comprises a capacitor capable of holding a charge and an access transistor for accessing the charge on the capacitor. Data bits are represented by the presence or absence of a charge on the capacitor. For example, a charge stored on the capacitor may correspond to a logical "1", while the absence of charge stored on the capacitor may correspond to a logical "0". Data can be stored in the memory cells during a write operation or retrieved from the memory cells during a read operation.
During a read operation, the desired memory cell is selected, or addressed. If the capacitor in the addressed memory cell is charged, then the capacitor discharges onto the bit line associated with the memory cell, which causes a change in the voltage on the bit line. On the other hand, if the capacitor in the addressed memory cell is not charged, then the voltage on the bit line associated with the memory cell remains constant. The change in voltage on the bit line (or lack thereof) can be detected to determine the state of the capacitor in the addressed memory cell, which indicates the value of the data bit stored in the memory cell.
A sense amplifier can be used to improve accuracy when determining the state of the capacitor in a particular cell. Typically, a sense amplifier includes a pair of n-channel transistors that have a cross-coupled gate and drain configuration and a pair of p-channel transistors that also have a cross-coupled gate and drain configuration. Due to the positive feedback of this transistor configuration, a sense amplifier can sense and amplify slight changes in the voltage on a bit line caused by the discharge of a capacitor onto the bit line.
Memory devices typically require a power supply, which provides a power supply voltage, referred to as V.sub.DD, to the components of the memory device. In general, the power consumption of a memory device is proportional to the value of V.sub.DD. Therefore, it is desirable to lower the value of V.sub.DD to conserve power in a memory device. Accordingly, device manufacturers are attempting to design memory devices with lower and lower values of V.sub.DD.
On the other hand, lowering the value of V.sub.DD can undesirably lengthen the response time of the sense amplifiers in a memory device or even cause the sense amplifiers to cease operating altogether. The response time of a sense amplifier is generally proportional to the amount of overdrive on the transistors in the sense amplifier. The overdrive on a transistor is controlled by the voltage potential between the gate and the source of the transistor, referred to as V.sub.GS, in excess of the threshold voltage required to activate the transistor, referred to as V.sub.T. In a typical memory array, the voltage on a bit line, referred to as V.sub.BL, corresponds to V.sub.GS for the transistors in the sense amplifier associated with the bit line. Furthermore, the value of V.sub.BL is proportional to the value of V.sub.DD. Therefore, the value of V.sub.DD affects the overdrive on the transistors in a sense amplifier, which in turn affects the performance of the sense amplifier. As the value of V.sub.DD is lowered, the overdrive on the sense amplifier transistors in the memory array is reduced, which undesirably lengthens the response time of the sense amplifiers.